BCS=0, MSEL=00, BCP=0, BCD=0, BCI=0, SYNC=00
SAI Transmit Configuration 2 Register
| DIV | Bit Clock Divide |
| BCD | Bit Clock Direction 0 (0): Bit clock is generated externally in Slave mode. 1 (1): Bit clock is generated internally in Master mode. |
| BCP | Bit Clock Polarity 0 (0): Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge. 1 (1): Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge. |
| MSEL | MCLK Select 0 (00): Bus Clock selected. 1 (01): Master Clock (MCLK) 1 option selected. 2 (10): Master Clock (MCLK) 2 option selected. 3 (11): Master Clock (MCLK) 3 option selected. |
| BCI | Bit Clock Input 0 (0): No effect. 1 (1): Internal logic is clocked as if bit clock was externally generated. |
| BCS | Bit Clock Swap 0 (0): Use the normal bit clock source. 1 (1): Swap the bit clock source. |
| SYNC | Synchronous Mode 0 (00): Asynchronous mode. 1 (01): Synchronous with receiver. 2 (10): Synchronous with another SAI transmitter. 3 (11): Synchronous with another SAI receiver. |